USPTO Patents Application 09847981

IN THE CLAIMS

This listing of claims will replace all prior versions, and listings, of claims in the application:

1 1 . (Previously presented) A computer system having a plurality of resources, comprising:

2 a first processor coupled to a first bus;

3 a second processor coupled to a second bus; and

4 an instruction memory coupled to the first bus and the second bus and having a software

5 direct memory access (DMA) engine stored therein, wherein

6 the software DMA engine is adapted to be executed by a processor of the first and

7 second processors, the processor being coupled to the first bus and the second

8 bus, and wherein

9 the software DMA engine is capable of transferring data directly between all of

10 the plurality of resources, each of the plurality of resources being connected to

11 at least one of the first bus and the second bus.

1 2. (Previously Presented) The system of Claim 1, wherein transferring data includes one or

2 more of data processing, data filtering, data compacting and data reformatting.

1 3. (Original) The system of Claim 2, wherein the resources comprise one or more of static

2 random access memory, dynamic random access memory and one or more hardware buffers that

3 are capable of interfacing with one or more peripheral devices.

1 4. (Previously Presented) The system of Claim 3, wherein the one or more hardware buffers,

2 in combination with the software DMA engine, permit the one or more peripherals to access the

3 memory directly.

1 5. (Previously Presented) The system of Claim 3, wherein the software DMA engine

2 comprises one or more instructions, the one or more instructions including a store multiple data

3 instruction and a load multiple data instruction wherein, when executed by the processor:
. 4 the load multiple data instruction loads data from multiple locations in one of the

5 hardware buffers into multiple locations in the internal registers in the processor, and

6 the store multiple data instruction transfers the data from multiple locations in the internal

7 registers into multiple locations in a memory.

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1 6. (Previously presented) A direct memory access (DMA) apparatus implemented in

2 software on a computer system, the computer system having two or more processors and a

3 memory coupled to each of the two or more processors, the DMA apparatus comprising:

4 a first instruction memory location in the computer system with a load multiple data

5 instruction loaded therein; and

6 a second instruction memory location in the computer system with a store multiple data

7 instruction loaded therein, wherein

8 the load multiple data instruction, when executed by a processor in the computer

9 system, is capable of loading data from multiple locations in a resource into

10 multiple locations in an intemal register in the processor; and

1 1 the store multiple data instruction, when executed by the processor in the

12 computer system, is capable of storing data from multiple locations in the

13 intemal register in the processor into multiple locations in a memory.

1 7. (Original) The apparatus of Claim 6, wherein the resources comprise one or more of

2 static random access memory, dynamic random access memory and one or more hardware

3 buffers that are capable of interfacing with one or more peripheral devices.

1 8. (Previously Presented) The apparatus of Claim 7, wherein the one or more hardware

2 buffers, in combination with the DMA apparatus, permit the one or more peripherals to access

3 the memory directly.

1 9. (Previously Presented) The apparatus of Claim 6, wherein the store multiple data

2 instruction and the load multiple data instruction, when executed by the processor, each further

3 include one or more of data processing, data filtering, data compacting and data reformatting.

10. (Canceled).